Analog Defect Injection and Fault Simulation Techniques: A Systematic Literature Review

Since the last century, the exponential growth of the semiconductor industry has led to the creation of tiny and complex integrated circuits, e.g., sensors, actuators, and smart power. Innovative techniques are needed to ensure the correct functionality of analog devices that are ubiquitous in every smart system. The ISO 26262 standard for functional safety in the automotive context specifies that fault injection is necessary to validate all electronic devices. For decades, standardization of defect modeling and injection mainly focused on digital circuits and, in a minor part, on analog ones. An initial attempt is being made with the IEEE P2427 draft standard that started to give a structured and formal organization to the analog testing field. Various methods have been proposed in the literature to speed up the fault simulation of the defect universe for an analog circuit. A more limited number of papers seek to reduce the overall simulation time by reducing the number of defects to be simulated. This literature survey describes the state-of-the-art of analog defect injection and fault simulation methods. The survey is based on the Preferred Reporting Items for Systematic Reviews and Meta-Analyses (PRISMA) methodological flow, allowing for a systematic and complete literature survey. Each selected paper has been categorized and presented to provide an overview of all the available approaches. In addition, the limitations of the various approaches are discussed by showing possible future directions

Nanoelectronic COupled problems solutions - nanoCOPS: modelling, multirate, model order reduction, uncertainty quantification, fast fault simulation

The FP7 project nanoCOPS derives new methods for simulation during development of designs of integrated products. It covers advanced simulation techniques for electromagnetics with feedback couplings to electronic circuits, heat and stress. It is inspired by interest from semiconductor industry and by a simulation tool vendor in electronic design automation. The project is on-going and the paper presents the outcomes achieved after the first half of the project duration

Modelling and characterisation of the SOI MOSFET for MMIC applications

Doctorat en sciences appliquées - UCL, 199

Scaleable equivalent circuit modelling of the EM field coupling to microstrips in the TEM cell

A scalable circuit model of the electric and magnetic field coupling to microstrips placed on the top wall of a TEM cell is presented. The coupling parameters have been derived using approximating equations to reduce simulation times as much as possible. Simulation results of the resulting circuit model are validated by S-parameter measurements.status: publishe

Scaleable equivalent circuit modelling of the E-field coupling to microstrips in the TEM cell

This investigation focuses on setting up a discrete model of the coupling between a TEM field generated inside a TEM cell to a device under test for use in a circuit simulator. In first instance, different microstrips are used as device under test because of their well-defined characteristics. The resulting models of the TEM cell, the microstrips and the electric field coupling between them are explained. Comparison and validation by measurements is presented for all models.status: publishe

Impact of lateral non-uniform doping and hot carrier degradation on capacitance behavior of high voltage MOSFETs

In this work, a detailed analysis of capacitance behavior of high voltage MOSFET (HV-MOS) e.g. LDMOS, VDMOS using device simulation is made. The impact of lateral non-uniform doping and drift region is separately analyzed. It is shown that the peaks in C-GD and C-GS capacitances of HV-MOS originate from lateral non-uniform doping. The drift region decreases the C-GD capacitance and increases the peaks in CGS and also gives rise to peaks in C-GG capacitances increasing with higher drain bias. It is also shown that trapped charge due to hot carrier degradation modulates (or introduce) the peaks amplitude and position in capacitances depending on hot hole or electron injection at drain or source side. This capacitance analysis will facilitate in optimization of the HV-MOS structure and also help in modeling of HV-MOS, including the hot carrier degradation

Equivalent Circuit Model of the TEM Cell Electric and Magnetic Field Coupling to Microstrip Lines

Electromagnetic compatibility (EMC) analysis of high-speed circuits is becoming mandatory due to the rapid increase in operating frequencies, RF interference and layout densities. Radiated susceptibility tests are important part of overall EMC analysis. In this paper the focus of investigation is on models of the coupling between a transverse electromagnetic (TEM) field generated by the TEM cell and the microstrip lines. In order to accurately model the coupling the models for microstrip lines, SMA connectors and TEM cell are developed. The coupling models are provided for transversal and longitudinal microstrip lines. The results for coupling capacitances are compared against results obtained by Method of Lines (MoL). The presented models are very accurate and include only passive elements, and therefore can be used for efficient coupling modelling between microstrip lines and the TEM cell septum.status: accepte

Verilog-A Implementation of Generic Defect Templates for Analog Fault Injection

With functional safety being increasingly important in the development of mixed-signal products for automotive applications, EDA solutions have appeared striving to help designers in the setup and execution of fault injection campaigns. Despite the ongoing work to standardize the definition of defect models and coverage calculation methods in the IEEE P2427 draft standard, there is a lack of a unified and portable method to define defect templates that can be used to inject in a systematic way defects in an analog circuit. Each of the existing EDA tool sets for fault injection proposes its own proprietary method to specify how defects should be defined and injected. The proposed paper describes a Verilog-A-based approach to coding defect templates, which through compliance with the Verilog-A standard, warrants portability across compatible simulators. The approach has been validated on the circuits from the Analogue Benchmark Circuits made available by the IEEE P2427 working group